Training

Module 1. Hardware Design in Xilinx: Vivado and the DPU IP Core

In this module, we will explain from scratch how to carry out a design using Vivado, delving into the most important features of this software. Likewise, the Xilinx DPU IP core will be introduced, and its characteristics will be explored in detail. This module also includes the creation of a design using this IP core.

• Introduction to Vivado

• Introduction to the Zynq UltraScale+ MPSoC Processing System IP Core

• Introduction to the DPU IP Core

• Hardware design with the DPU

Module 2. Introduction to Petalinux

In this module, everything related to the Petalinux tool will be explained: how to create, customize, and deploy a tailored Linux distribution for embedded hardware on the Xilinx processing subsystem (PS).

• Introduction and configuration of Petalinux from scratch

• Fundamentals of the Device Tree

Module 3. Designing a Python Application with Vitis AI for the DPU

• Introduction to neural network optimization (quantization)

• Introduction to the Xilinx DPU (capabilities, benchmarks, requirements)

• Overview of the Ultra96 platform

• Training a neural network model (should have been done in the previous module)

• Quantization and compilation of a neural network model with Vitis AI

• Development of a real-time application using the compiled model with Vitis AI

Digital Signal Processing (DSP) is at the core of modern communication, vision, and control systems. In this seminar, we will explore how AMD FPGA and Adaptive SoC platforms can be leveraged to implement DSP algorithms efficiently. We will compare design methodologies, highlighting the strengths and trade-offs of different implementation approaches.

Using Vitis HLS and Vitis Model Composer, we will walk through practical examples that demonstrate how algorithm developers can accelerate the path from floating-point models to optimized hardware-ready designs. The session will cover:

• Key considerations when mapping DSP algorithms to programmable logic or AI Engines.
• High-level design entry with C/C++ and MATLAB/Simulink flows.
• Performance, resource utilization, and design productivity trade-offs.

• Practical tips for debugging and optimizing DSP workloads on AMD devices.
• SoC partitioning strategies: deciding what runs in PL, PS, or AI Engines, and optimizing AXI and NoC bandwidth.

By the end of the talk, attendees will gain a clear understanding of how to harness FPGA and Adaptive SoC capabilities for DSP applications, bridging the gap between algorithm development and hardware acceleration.

This course introduces software developers to the options and techniques for selecting and implementing various types of operating systems and hypervisors on AMD Zynq UltraScale+ MPSoC and Versal devices.

This introductory course lays the foundations for efficient work using the UVM methodology. The first part of the course begins with a review of SystemVerilog, assuming prior knowledge of Verilog. The second part establishes the core UVM concepts and develops the set of guidelines and recommended practices for building efficient testbenches.

Part I: Introduction to SystemVerilog

• Verification of digital systems today

• From Verilog to SystemVerilog: improvements over Verilog

• Array types: multidimensional, associative, dynamic, queues — and the concept of the scoreboard associated with their use

• Concurrency, threads, and inter-process communication: fork, join, disable, events, semaphores, mailboxes

• SVA (SystemVerilog Assertion Language)

• RCSG: Random Constraint Stimulus Generation

• Code coverage and functional coverage

• Basic SystemVerilog OOP; use of packages

• Verification workflow: vPlan, regressions, bug reporting and bug tracking; directed tests, randomized tests, error injection, stress testing

Part II: Basic UVM

• Basic concepts of UVM (Universal Verification Methodology)

• Testbench structure: interfaces, use of interfaces in testbenches, use of clocking blocks

• Advanced SystemVerilog OOP

• Transactions and sequences

• Drivers and sequencers

• Monitors and agents

• Coverage collectors

• Scoreboard and environment

• Configuration and factory

• UVM tests and complex sequences